1. Field of the Invention
The invention relates to the resetting of digital circuits, and more particularly to integrated circuits generating self-timed power-on-resets without use of external timing elements or digital counters.
2. Description of the Related Art
A power-on-reset signal is required by digital circuits involving memory elements or flip-flops to set the initial state immediately after power on. This signal was traditionally generated externally using an external RC circuit or simply by a switch, the latter requiring manual intervention.
The problem of integrating the first technique was with the rate of rise of the power supply, which is usually very slow. As a result, the RC time constant needs to be very large for successful generation of a power-on-reset signal. Realization of such high time constants on chip takes up too much space to be practically viable, although the same may be easily realized externally.
Three U.S. Patent have been issued dealing with the power-on-reset circuits.
U.S. Pat. No. 5,300,822 (Sugahara, et al.) is somewhat similar to the invention in that a power-on-reset signal is provided once the supply voltage reaches the sum of V.sub.TN and V.sub.TP, however, the circuit differs from that of the invention.
U.S. Pat. No. 5,172,012 (Ueda) provides a power-on-reset circuit which provides a POR output signal independently of the rises time of the supply voltage, but in a different way from the invention.
U.S. Pat. No. 5,483,187 (Jang) describes a power-on-reset circuit which also outputs a reset pulse regardless of the supply voltage rise rate, but using a Schmitt trigger and state latch circuit.